In the semiconductor industry, a gate stack including a high-k gate dielectric (a gate dielectric having a dielectric constant of greater than 4.0, typically greater than 7.0) and a metal gate is one of the most promising options for continuing complementary metal oxide semiconductor (CMOS) scaling.
One of the process schemes for fabricating a high-k/metal gate MOSFET is a replacement gate method. In a replacement gate process, a MOSFET can be fabricated using a sacrificial gate electrode. In such a process, the sacrificial gate electrode is formed first and thereafter the sacrificial gate electrode is replaced by a gate stack including a high-k gate dielectric and a metal gate. Since the gate stack including the high-k gate dielectric and the metal gate is formed after high temperature processing steps such as a source/drain activation anneal, the replacement gate process has the advantage of minimal damage on the high-k gate dielectric and the metal gate. Moreover, a wide range of metals can be selected for the gate conductor.
One severe drawback of a conventional gate replacement process results in the high-k gate dielectric being present not only beneath the metal gate, but also on vertical sidewalls of the metal gate.
FIG. 1 is a pictorial representation of a prior art MOSFET including a gate stack comprising a high-k gate dielectric and a metal gate which is fabricated using a conventional gate replacement process as mentioned above. In particular, FIG. 1 shows a prior art MOSFET structure that includes a semiconductor substrate 1000 that has source/drain diffusion regions 1004 located therein. The semiconductor substrate 1000 also contains trench isolation regions 1006 that are filled with a trench dielectric material. Atop the semiconductor substrate 1000, there is shown a high-k gate dielectric 1008, which is formed in the shape of a “U”, and a metal gate 1010 located within the U-shaped high-k gate dielectric 1008. A dielectric spacer 1012 is located on outer vertical sidewalls of the U-shaped high-k gate dielectric 1008. The structure shown in FIG. 1 also includes an interlevel dielectric material 1020 that has contact vias 1022 located therein which extend to the upper surface of the source/drain diffusion regions 1004. The interlevel dielectric material 1020 is laterally separated from the gate stack by the dielectric spacer 1012.
The presence of the metal gate 1010 on the vertical sidewalls of the U-shaped high-k gate dielectric 1008 results in an undesired high contact-to-gate conductor parasitic capacitance.
Another problem associated with a high-k gate dielectric is that the high-k gate dielectric at the gate corners (represented by the dotted circle shown in FIG. 1) may not be ideal due to variations in thickness and/or chemical component. A conventional gate reoxidation process cannot be used to strengthen the high-k gate dielectric at the gate corners because the high-k gate dielectric is sealed by the metal gate and the dielectric spacer. The non-ideal high-k gate dielectric at the gate corners results in high leakage and poor reliability.
In view of the above, there is a need for a new and improved high-k/metal gate MOSFET with reduced contact-to-gate conductor parasitic capacitance and, optionally, an improved high-k gate dielectric at the gate corners.